The silicon bipolar transistor has been the device of choice for high power applications in motor drive circuits, appliance controls, robotics and lighting ballasts. This is because bipolar transistors can be designed to handle relatively large current densities in the range of 40-50 A/cm.sup.2 and support relatively high blocking voltages in the range of 500-1,000 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications. First of all, bipolar transistors are current controlled devices which require relatively large base currents, typically one fifth to one tenth of the collector current, to maintain the transistor in an operating mode. Proportionally larger base currents can be expected for applications which also require high speed turn-off. Because of the large base current demands, the base drive circuitry for controlling turn-on and turn-off is relatively complex and expensive. Bipolar transistors are also vulnerable to premature breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications. Furthermore, it is relatively difficult to parallel connect bipolar transistors because current diversion to a single transistor typically occurs at high temperatures, making emitter ballasting schemes necessary.
The silicon power MOSFET was developed to address this base drive problem. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias. For example, turn-on in an N-type enhancement MOSFET occurs when a conductive inversion layer is formed in the P-type channel region in response to the application of a positive gate bias. The inversion layer electrically connects the N-type source and drain regions. As will be understood by one skilled in the art, the length of the channel in a vertical power MOSFET is dependent on the rate of diffusion of the source and channel dopants in the silicon substrate. The length of the channel is an important design parameter because it has a strong influence on the MOSFET's on-resistance and transconductance.
The power MOSFET's gate electrode is separated from the channel region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the channel region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET's channel region. Thus, only charging and discharging current ("displacement current") is required during switching. Because of the high input impedance associated with the insulated gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented. Examples of known power MOSFETs such as the DMOSFET and UMOSFET structures of FIGS. 1 and 2 respectively, are described in a textbook by inventor Baliga, entitled Modern Power Devices (1987), beginning at Chapter 6, and an article by Syau, Venkatraman and inventor Baliga, entitled Extended Trench-Gate Power UMOSFET Structure with Ultralow Specific On-Resistance, published in Electronics Letters, Vol. 28, No. 9, pp. 865-867 (1992). However, both of these devices contain a P-N junction diode between the source and drain regions. As will be understood by those skilled in the art, the presence of a P-N junction can interfere with high frequency applications such as synchronous rectification because of the delay caused by minority carrier recombination when the MOSFET switches from the on-state to the off-state.
An example of a silicon power MOSFET for use in synchronous rectification applications is shown in FIG. 3. FIG. 3 is a reproduction of FIG. 4 from U.S. Pat. No. 4,903,189 to Ngo et al. and inventor Baliga, the disclosure of which is hereby incorporated herein by reference. This MOSFET 170, which includes trenches 178 at a face thereof and contains no P-N junctions, is commonly referred to as an accumulation-mode FET ("ACCU-FET") because turn-on is achieved by forming a conductive accumulation layer between the FET's source 186 and drain 182 regions. FIG. 3 shows a plurality of parallel connected ACCU-FET cells, each defined by mesas 179 and opposing trenches 178.
The ACCU-FET's on-state resistance is an important design parameter. The higher the on-state resistance, the higher the forward voltage drop and the higher the forward power losses. The on-state resistance of an ACCU-FET cell is dependent on the combined series resistance of the source, drift and drain regions. As will be understood by those skilled in the art, the series resistance of the drift region 184 includes the parallel contribution of each of the accumulation layers, which extend along opposing trench sidewalls when an appropriate polarity gate bias has been applied.
For an ACCU-FET of solely N-type conductivity, the width of the mesas and the drift region doping concentration can be chosen so that a potential barrier between the source 186 and drain 182 regions will be formed at zero potential gate bias. The potential barrier can be made sufficiently high to prevent conduction between the source and drain at relatively high blocking voltages. As will be understood by those skilled in the art, the ACCU-FET's maximum blocking voltage capability is a function of the height of the potential barrier between the source and drain and the thickness of the oxide 195 in the trench. Thicker oxides typically cause an increase in blocking voltage capability, however, thicker oxides result in higher forward conduction losses for a given gate bias. Blocking voltages of 50 Volts can be obtained with relatively low drift region 184 doping concentrations of 5.times.10.sup.13 /cm.sup.3.
Higher blocking voltages can be expected with lower drift region doping concentrations. Unfortunately, attempts to increase the blocking voltage capability to above 50 Volts will typically eliminate the benefits of using an accumulation layer channel by making the on-state resistance in the drift region 184 too high. The silicon ACCU-FET of FIG. 3 can be designed for low forward power consumption by making the drift region doping concentration relatively high, but can be designed to support relatively high blocking voltages by making the drift region doping concentration relatively low. In other words, there is a competing tradeoff between designing for low forward power consumption and high blocking voltage capability.
Therefore, notwithstanding the recognized use of power MOSFETs for applications requiring high-speed turn-off and low gate-drive currents, there continues to be a need for a power MOSFET capable of sustaining high blocking voltages with low on-state resistance and which can be used for high frequency applications such as synchronous rectification and high power applications such as motor control.